1. Field of the Invention
The present invention relates to digital signal processing, and more particularly, to a conditional select adder of a digital signal processor which can reduce current consumption and delay time, and a method therefor. The present invention is based on Korean Patent Application No. 2002-2538, which is incorporated herein by reference.
2. Description of the Related Art
Recently, circuit design technology for high speed multi-bit addition or multiplication has become important for performing calculation functions in a high-speed Digital Signal Processor (DSP). Among the calculations, addition is one of the essential operations of data path blocks in a computer system or a microprocessor system, and has a great influence on the speed performance of a system. In the prior art, current consumption and delay time in calculation are not satisfactory. Also, in recent ultra precision processes, delay time due to wiring is more important than cell delay time, and therefore it is necessary to design a circuit so as to reduce internal wiring of an adder.
FIG. 1 is a schematic diagram of a prior art 64-bit conditional select adder 100. Referring to FIG. 1, the conditional select adder 100 has a plurality of conditional selection addition modules 110 through 180, each of which generates a carry by analyzing input values to be added, and calculates a sum according to the presence of the carry, and a block carry generating block 190 which, in response to the carries generated by the conditional selection addition modules, determines the presence of the carry and feeds the result back to the conditional selection addition module.
Each of the conditional select addition modules 110 through 180 has a pre-carry-sum generating block 112 which analyzes input values to be added and generates appropriate values in advance, a sum generating block 114 which obtains a limit of the value generated by the pre-carry-sum generating block 112, but obtains a sum in each case according to the presence of a carry, and a carry generating block 116 which obtains a carry in response to a value generated by the pre-carry-sum generating block 112.
The pre-carry-sum generating block 112 of a first conditional select addition module 110 analyzes input values to be added in the first conditional select addition module 110, and adds an appropriate value in advance. At this time, the sum generating block 114 generates a sum when there is a carry and a sum when there is no carry, and the carry generating block 116 outputs the carry of the first conditional select addition module 110 to the block carry generating block 190.
Also, the pre-carry-sum generating blocks of the remaining conditional select addition modules 120 through 180 analyze input values to be added in the respective conditional select addition modules 120 through 180, and perform addition with appropriate values in advance. At this time, the sum generating block generates a sum when there is a carry, and a sum when there is no carry, and the carry generating block outputs the carry of each conditional select addition module to the block carry generating block 190.
The block carry generating block 190 receives carries from 8-bit conditional select additional modules 110 through 180 and feeds the presence of a carry back to the conditional select addition module of the next stage. As a result, the appropriate sum according to the presence of a carry is selected from among sums which are calculated in advance in the sum generating block of each of the 8-bit conditional select addition modules 110 through 180.
FIG. 2 is a block diagram of the sum generating block 114 of the 8-bit conditional select adder module shown in FIG. 1. The sum generating block 114 shown in FIG. 2 is formed with multiplexers using Pass Transistor Logic (PTL) based on an NMOS transistor, and uses Level Restore Blocks (LRBs) appropriate to the driving capability of a multiplexer for low power consumption and high speed operation. Here, M denotes a multiplexer, S denotes single, D denotes double, and L denotes a level restore block. For example, MS means a single multiplexer, and MDL means a double multiplexer having a level restore block.
FIG. 3 is a block diagram of a carry generating block 116 of the 8-bit conditional select adder module shown in FIG. 1, and FIG. 4 is a block diagram of a block carry generating block 190 shown in FIG. 1.
As shown in FIGS. 1 through 3, in the prior art adder, a carry is calculated in both the sum generating block 114 and the carry generating block 116. Therefore, since separate carry generating logic must be designed into the sum generating block 114, wiring becomes complicated and more logic is used. Also, in the prior art adder as shown in FIG. 5, in order to calculate a carry in the carry generating block 116, XNOR, XOR, AND, NAND, OR, and NOR logic operations are needed, and the pre-carry-sum generating block 112 includes logic gates such as XNOR, XOR, AND, NAND, OR, and NOR. Therefore, fan-outs of input signals ‘X, Y’ increase and wiring becomes complicated.
Also, since the prior art adder is based on PTL, wiring must be complicated in order to calculate a carry and a sum, and physical wire delay increases the overall delay time and consumes more space. In addition, since PTL is used, an inverted signal is always needed, which increases wiring and power consumption. Also, the block carries (BC0, BC1, BC2, BC3, BC4, BC5, BC6, and BC7) generated in the block carry generating block 190 shown in FIG. 4 are not output in synchronization, and therefore the generation of sums in the respective modules are also not synchronized.